2020_Session C

Session C - RADIATION EFFECTS IN DEVICES AND INTEGRATED CIRCUITS

Wednesday, December 2, 2020
All times Eastern Standard Time

SESSION C
10:00 AM - 12:30 PM
Room 3

RADIATION EFFECTS IN DEVICES AND INTEGRATED CIRCUITS
SESSION INTRODUCTION
Chair: Randall Milanowski, Milanowski & Associates

C-1

Depth Dependence of Threshold Voltage Shifts in 3D Flash Memories Exposed to X-rays.
M. Bagatin, A. Paccagnella, University of Padova, Italy, S. Gerardin, DEI - University of Padova, Italy, B. Silvia, Micron Technology, Italy

The effects of total ionizing dose on 3D floating gate cells are analyzed as a function of depth. Due to the manufacturing process and geometry of the pillars, shifts are larger at the bottom.

C-2

Heavy Ion Irradiation Effects on Perpendicular-Anisotropy Spin-Orbit-Torque Magnetic Tunnel Junctions
M. Alamdar, L. Chang, C. Cui, Y. Liu, E. Antunano, J. Incorvia, University of Texas at Austin, USA, J. Manuel, G. Vizkelethy, , R. Jacobs-Gedrim, C. Bennett, T. Xiao, D. Hughart, E. Bielejec, M. Marinella, Sandia National Laboratories, USA, L. Xue, Applied Materials, USA

We study the impact of heavy ion irradiation on magnetic tunnel junctions with perpendicular magnetic anisotropy and spin orbit torque switching. We show how the domain structure and magnetic material behavior depend on irradiation fluences.

C-3

Structures for Characterizing TID-induced inter-device leakage in 14nm Bulk FinFET Technologies
A. Privat, H. Barnaby, L. Clark, J. Brunhaver, D. Alen, K. Holbert, Arizona State University, USA, M. McLain, M. Matt, M. King, Sandia National Laboratories, USA

The total ionizing dose response of 14nm bulk-Si FinFETs has been studied with specially designed test chips containing several logic gates. TCAD simulations were performed and are consistent with the experimental data.

C-4

Total Ionizing Dose Response of 22 nm FDSOI Charge-Trap Transistors
R. Brewer, D. Ball, B. Sierawski, P. Wang, E. Zhang, D. Fleetwood, R. Schrimpf, M. Alles, Vanderbilt University, USA, J. Cox, S. Moran, S. Iyer, University of California Los Angeles, USA

Total ionizing dose effects are investigated for 22 nm FDSOI charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state. Hole trapping in the buried oxide dominates the TID response.

C-5

Combined Total Ionizing Dose and Single-Event Effects on a 22 nm Fully-Depleted Silicon-on-Insulator Test Vehicle
M. Casey, J. Pellish, NASAGSFC, USA, S. Stansberry, Science Systems and Applications, Inc.), USA

Total ionizing dose irradiations were performed on a 22 nm fully-depleted silicon on insulator static random access memory. There is a strong well-bias effect in the TID response. Combined TID and SEE results are also presented.

C-6

Total-Ionizing-Dose Response of Highly-Scaled Gate-All-Around Si Nanowire CMOS Transistors
M. Gorchichko, E. Zhang, P. Wang, R. Schrimpf, R. Reed, D. Fleetwood, Vanderbilt University, USA, S. Bonaldo, University of Padova, Italy, D. Linten, J. Mitard, IMEC, Belgium

The total-ionizing-dose response of GAA Si NW CMOS transistors is investigated under different bias conditions. Devices demonstrate outstanding ionizing radiation tolerance due to enhanced electrostatic control and suppression of parasitic leakage current paths.

C-7

Ultra-High Total Ionizing Dose Effects on MOSFETs for Analog Applications
H. Dewitte, V. Goiffon, ISAE-SUPAERO, France, S. Rizzolo, Airbus Defence and Space, France, P. Paillet, C. Marcandella, CEA, France

The influence of the bias, the gate thickness and the rad-hard designs (ELTs, Butterflies,...) on the apparition of effects such as RINCE, RISCE, Gate-induced or source to drain leakages is studied for MOSFETs under high-TID.

C-8

Donor- and Acceptor-Like Defects in Irradiated AlGaN/GaN HEMTs
P. Wang, X. Li, E. Zhang, M. McCurdy, R. Schrimpf, D. Fleetwood, Vanderbilt University, USA

Donor- and acceptor-like defects are observed during 10-keV and 1.8-MeV irradiations of AlGaN/GaN HEMTs. ON donors dominate the response at low fluence, and VN-related acceptors dominate at high fluence.

C-9

Defect Densities and Energies in As-Processed and Irradiated Fully-Depleted Silicon on Insulator MOSFETs Fabricated Using 3D Sequentially Integrated Technology
S. Toguchi, E. Zhang, P. Wang, D. Fleetwood, R. Schrimpf, R. Reed, M. Alles, Vanderbilt University, USA, S. Moreau, S. Cheramy, P. Batude, L. Brunet, F. Andrieu, CEA-LETI, France

Added thermal cycles associated with forming upper-layer transistors via 3D sequential integration do not significantly affect post-irradiation densities of oxide, interface, or border traps of FD SOI transistors built in the lower stack layer.

Tuesday, December 8, 2020

10:00 AM - 1:00 PM

POSTER SESSION
Chair: Andrew Sternberg, Vanderbilt University

PC-1

Total Ionization Dose Effects on NAND Flash Memory Based Physical Unclonable Function
S. Sakib, B. Ray, The University of Alabama in Huntsville, Huntsville, AL, USA

We investigate the total ionization dose (TID) effects on flash memory-based physically unclonable functions (PUFs). We find that flash-PUF accuracy degrades significantly with TID~10 krad. We proposed an electrical-annealing technique to improve the PUF accuracy.

PC-2

An Ionizing-Dose-Aware Behavioral Model of a Successive-Approximation Analog to Digital Converter
M. Rony, E. Zhang, M. Reaz, K. Li, R. Reed, J. Kauppila, A. Witulski, R. Schrimpf, Vanderbilt University, USA, B. Rax, A. Daniel, P. Adell, NASA-JPL, USA

ADCs of different structures respond differently to Total Ionization Dose (TID). Dynamic gain and dynamic offset are the key parameters that are sensitive to TID in successive-approximation-register (SAR) ADCs.

PC-3

Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment
D. Soderstrom, University of Jyväskylä, Finland, L. Matana luza, L. Dilillo, LIRMM, France, H. Kettunen, A. Javanainen, RADEF, Finland, W. Farabolini, A. Coronetti, CERN, Switzerland, C. Poivey, ESA, Netherlands

This study investigates the response of SDRAMs to electron irradiation. Stuck bits, SEUs and memory cell degradation is presented in this paper, in a memory that will be part of the ESA JUICE mission.

PC-4

Investigating Heavy Ion Effects on 14 nm-Process FinFETs: Displacement Damage Versus Total Ionizing Dose
M. Esposito, J. Manuel, E. Bielejec, G. Vizkelethy, J. Dickerson, P. Kerber, M. King, A. Tali, D. Ashby, M. McLain, M. Marinella, Sandia National Laboratories, USA, A. Privat, H. Barnaby, J. Brunhaver, Arizona State University, USA

Heavy ion irradiation was examined on a commercial 14-nm n-type FinFET technology to investigate displacement damage and total ionizing dose effects. Low temperature measurements were conducted to reveal underlying physics.

PC-5

Gamma Ray Induced Error Pattern Analysis for MLC 3D-NAND
U. Surendranathan, B. Timothy, B. Ray, The University of Alabama in Huntsville, USA

Data corruption rate on the shared pages of MLC 3-D NAND under Co-60 Gamma rays (20-krad) shows a unique correlated behavior. The error location within a given page remains uncorrelated.

PC-6

Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs
K. Li, E. Zhang, M. Gorchichko, P. Wang, S. Zhao, M. Alles, R. Reed, D. Fleetwood, R. Schrimpf, Vanderbilt University, USA, G. Hiblot, S. Huylenbroeck, A. Jourdain, IMEC, Belgium

Total-ionizing-dose effects and low-frequency noise are evaluated in advanced bulk FinFETs with and without TSV via-last integration. The presence of the TSVs does not affect threshold voltage, Ion/Ioff, or noise.

PC-7

Influence of Total Ionizing Dose on Magnetic Tunnel Junctions with Perpendicular Anisotropy
B. Zink, J. Wang, J., University of Minnesota, USA, Yang-Scharlotta, M. Han, NASA-JPL, USA, F. Mancoff, J. Sun, Everspin Technologies., USA

Spin-transfer torque magnetic random-access memory (STT-MRAM) is a promising solution for onboard, radiation-tolerant memory. In this study, we examine the effect of TID exposure on the MTJ’s thermal stability and its critical switching voltage.

PC-8

Total Ionizing Dose Effects on Multi-state HfOx-based RRAM Synaptic Arrays
X. Han, A. Privat, K. Holbert, J. Seo, H. Barnaby, Arizona State University, USA, S. Yu, Georgia Institute of Technology, USA

The impact of total ionizing dose on the multi-states of HfOx-based RRAM is investigated by irradiating the 1-transistor-1-resistor 64kb array with CMOS peripheral decoding circuitry fabricated at 90 nm node.

PC-9

Foundry Dependence of Total Ionizing Dose Effects of FinFET Transistor in 14-nm Technological Node
L. Artola, T. Chiarella, T. Nuns, G. Cussac, ONERA, France, J. Mitard, IMEC, Belgium

This work presents a new set of data of TID responses under Co60 irradiation. Process dependences of degraded transistor operating characteristics are quantified as a function of three different manufacturer lines of 14-nm FinFET technology.

PC-10

Comparison of TID-induced Degradation of Programmable Logic Timing in Bulk 28 nm and 16 nm FinFET System-on-Chips under Local X-ray Irradiation
I. Lopes, V. Pouget, F. Wrobel, A. Touboul, F. Saigné, J. Boch, T. Maraine, University of Montpellier 2, France, K. Roed, University of Oslo, Norway

This paper presents the comparison of TID-induced timing degradation of two system-on-chip generations. The degradation was analyzed using local X-ray irradiation. Timing degradations for each technology were presented, compared and discussed.

PC-11L

Ionizing Radiation Effect in SONOS-based Neuromorphic Inference Accelerators
T. P. Xiao, C. H. Bennett, S. Agarwal, D. Hughart and M. Marinella, Sandia National Laboratories, USA; H. J. Barnaby, Arizona State University, USA, H. Puchner and V. Prabhakar, Infineon Memory Solutions - USA

The sensitivity of SONOS-based neuromorphic inference accelerators to total ionizing dose is evaluated. An experimentally validated model is proposed for the radiation response of SONOS synapses, and inference accuracy is simulated up to 1000 krad(Si)

PC-12L

Pre-charge Optimization in Sidewall Spacer Memory Bit Cell with Respect to Total Ionizing Dose
T. Vincenzi and G. Schatzberger, AMS AG, Austria, A. Michalowska Forsyth, Graz University of Technology, Austria

This paper analyses a charge-based Non-Volatile Memory device: the Sidewall Spacer. Multiple test-dies from a 55nm standard CMOS process are tested up to 500krad assessing data retention depending on charge injection in the nitride spacer.