2020_Session E

Session E - SINGLE EVENT EFFECTS: DEVICES AND INTEGRATED CIRCUITS

Thursday, December 3, 2020
All times Eastern Standard Time

SESSION E
10:00 AM - 12:30 PM
Room 6

SINGLE EVENT EFFECTS: DEVICES AND INTEGRATED CIRCUITS
SESSION INTRODUCTION
Chair: Georgios Tsiligiannis, University of Montpellier 2

E-1

Single-Event-Induced Charge Collection in Ge-Channel pMOS FinFETs
M. Rony, I. Samsel, E. Zhang, A. Sternberg, M. Reaz, S. Austin, R. Reed, D. Fleetwood, M. Alles, J. Mitard, R. Schrimpf, Vanderbilt University, USA, K. Li, D. Linten, IMEC, Belgium

Single-event charge collection in Ge-channel pMOS FinFETs exhibits a different spatial dependence than planar Ge pMOS devices. The total collected charge depends on applied gate bias, whereas the peak transient does not.

E-2

Electrical Measurement of Cell-to-Cell Variation of Critical Charge in SRAM and Sensitivity to Single-Event Upsets by Low-Energy Protons
J. Cannon, University of Tennessee at Chattanooga, USA and Macalester College, USA, R. Estrada, University of Tennessee at Chattanooga, USA, and New Mexico Institute of Mining and Technology, USA, R. Boggs, University of Tennessee at Chattanooga, USA and NASA GSFC, USA, B. Patel, G. Santos, T. Loveless, University of Tennessee at Chattanooga, USA, M. McCurdy, A. Sternberg, Vanderbilt University, USA, T. Finzell, Macalester College, USA

Low-energy proton irradiation of COTS SRAMs shows that SEU cross-sections near the LET threshold are dominated by nominally weak cells. An electrical procedure is presented to map cell critical charge values, allowing customized part usage.

E-3

Single-Event Upsets in a 7-nm Bulk FinFET Technology with Analysis of Threshold Voltage and Bias Dependencies
J. V. D’Amico, J. Cao, L. Xu, J. Kauppila, L. Massengill, Vanderbilt University, USA, B. Bhuva, M. Rathore, S. Wen, R. Fung, Cisco Systems, Inc., USA, B. Narasimham, Broadcom, Inc., USA

Single-event upset responses of D-FF designs with different threshold voltage (VT) options in a 7-nm bulk FinFET technology are evaluated. Results show that single-event cross-section depends heavily upon supply voltage and particle LET values.

E-4

Direct Ionization from Low-Energy Electrons in a Highly-Scaled CMOS Process
M. Casey, J. Pellish, NASA GSFC, USA, S. Stansberry, Science Systems and Applications, Inc., USA, M. Breeding, R. Reed, Vanderbilt University, USA

Low-energy-electron-induced single-event upsets are observed in a 22 nm fully-depleted silicon-on-insulator process at nominal and higher supply voltages. Electron dose enhancement was also observed.

E-5

Single-Event Latchup in a 7-nm Bulk FinFET Technology
C. Sheets, L. Xu, J. Cao, S. Ball, J. Kauppila, B. Bhuva, L. Massengill, Vanderbilt University, USA, R. Fung, S. Wen, Cisco Systems, Inc., USA, C. Cazzaniga, Rutherford Appleton Laboratories, United Kingdom

Single-event-induced latchup at the 7nm bulk FinFET node is characterized as a function of supply voltage and temperature. Results show the holding voltage as low as 0.85 V at elevated temperature.

E-6

Observation of Low-Energy Proton Direct Ionization in a 72-Layer 3D NAND Flash Memory
E. Wilcox, M. Casey, J. Pellish, NASA GSFC, USA

Single-event upsets are observed in a 72-layer 3D NAND flash memory operated in SLC mode with low-energy proton (500 keV-1.2 MeV) and heavy ion irradiation. Direct ionization by low-energy protons is analyzed three-dimensionally.

Tuesday, December 8, 2020

10:00 - 1:00 PM

POSTER SESSION
Chair: Andrew Sternberg, Vanderbilt University

PE-1

Updates on Testing Microprocessors Effectively
H. Quinn, Los Alamos National Laboratory, USA, K. Gnawali, S. Tragoudas, Southern Illinois University Carbondale, USA

Updates to the software benchmark for radiation testing mitigated software codes are presented. The updates include new memory testing algorithms, a new sorting algorithm, and an update to the standard matrix multiply code.

PE-2

Influence of Supply Voltage and Body Biasing on Single-Event Upsets and Single-Event Transients in UTBB FD-SOI
C. Lecat-Mathieu De Boissac, F. Abouzeid, V. Malherbe, G. Gasiot, P. Roche, STMicroelectronics, France, J. Autran, Aix-Marseille University, France

We present a study of single-event effects through supply voltage and body bias variations in 28 nm UTBB FD-SOI. Heavy ion experiments were performed, showing the variation of SEE sensitivity in both sequential and logic cells.

PE-3

Stuck-Bits Screening in a 512Mb SDRAM Induced by Proton and γ-Rays
S. Bounasser, C. Boatella Polo, T. Borel, C. Poivey, ESA, Netherlands

TID and Proton tests have been made in order to evaluate the SEU/SB/SEFI sensitivity of a 512Mb SDRAM. Roots-cause analysis of stuck-bits formation is discussed as well as the VRT phenomenon induced by proton irradiation.

PE-4

Microbeam Heavy Ion and Event Tree Analysis Investigating Single Event Effect Propagation in System-on-Chip
W. Yang, School of Nuclear Science and Technology, China and Politecnico di Torino, Italy, S. Azimi, B. Du, L. Sterpone, School of Nuclear Science and Technology, China, X. Du, Y. Li, C. He, S. Shuting, L. Cai, National Innovation Center of Radiation Application, China, G. Gant, Politecnico di Torino, Italy

This paper presents heavy ion induced SEE propagation on 28 nm System-on-Chip SRAM reconfigurable devices. Results obtained by microbeam radiation test show sensitivity location and cross-section for functional blocks such as ALU, user-registers, D-Cache and Peripherals.

PE-5

Developing Benchmarks for Radiation Testing of Microcontroller Arithmetic Units Using ATPG
K. Gnawali, S. Tragoudas, Southern Illinois University Carbondale, USA, H. Quinn, Los Alamos National Laboratories, USA

Reliability-focused benchmarks are used to test systems in harsh operating conditions. This paper proposes a mechanism to develop such benchmarks for radiation testing of microcontroller arithmetic and logical units using automatic test pattern generation (ATPG).

PE-6

Neutron-Induced Pulse Width Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain Based Test Structure
N. Pande, S. Kumar, L. Everson, G. Park, I. Ahmed, C. Kim, University of Minnesota, USA

This work presents measured data corresponding to neutron-induced pulse width distributions for standard logic gate types together with detailed analysis on the range of design choices impacting the former.

PE-7

Comparison of Low-Energy Proton-Induced Single-Event-Upsets in 7-nm and 14-/16-nm FinFET Flip-Flops
N. Ogden, A. Feeley-Lamb, Y. Xiong, B. Sierawski, R. Reed, B. Bhuva, J. Maharrey, R. Harrington, T. Haeffner, K. Warren, M. McCurdy, M. Howell, J. Kauppila, L. Massengill, Vanderbilt University, USA

Low-energy proton-induced upset data are presented for 7-nm and 14-/16-nm FinFET flip-flop shift-registers. The 7-nm flip-flop upset cross-section was less pronounced than 14-/16-nm, but larger at higher energies.

PE-8

Evaluating the Impact of Reducing Data Precision on the Reliability of Neural Networks on FPGAs
F. Libano, J. Brunhaver, Arizona State University, USA, P. Rech, Universidade Federal do Rio Grande do Sul, Brazil and Los Alamos National Laboratory, USA, B. Neuman, Los Alamos National Laboratory, USA, J. Leavitt, M. Wirthlin, Brigham Young University, USA

Through neutron beam experiments, we analyze how precision reduction of neural networks on FPGAs can effectively deliver lower radiation sensitivity, while maintaining high accuracy levels. We compare 32-bit to 16-bit floating-point and 8-bit integer implementations.

PE-9L

Heavy Ions Radiation Effects on 4kb Phase-Change Memory
A. L. Serra, G. Bourgeois, M. C. Cyrille, C. Charpin-Nicolle, G. Navarro and E. Nowak, CEA-LETI-MINATECH, France, T. Vogel, S. Petzold, N. Kaiser, L. Alff, Advanced Thin Film Technology, University of Darmstadt, Germany, G. Lefevre, C. Vallée and D. Sylvain, CNRS-LTM Laboratoire des Technologies de la Microelectronique, France, C. Trautmann, Material Research Department, Darmstadt GSI, Germany

In this work we analyze, thanks to both material and 4kb memory arrays characterization, the different effects of heavy ion radiation at high fluences on Ge2Sb2Te5 and Ge-rich GeSbTe based Phase-Change Memory (PCM).