Spanish Exploration and the Beginnings of Texas Natural History Dr. Jesús F. de la Teja, Chief Executive Officer, Texas State Historical Association
Spanish exploration of what is now Texas began in earnest in the late 17th century. Expeditions often were led by Franciscan missionaries looking for new opportunities to convert the native population to Christianity. They often were also the result of military efforts to repel imperial rivals. Aside from the rich record of the Indian peoples of the region, the journals and diaries of expeditions across the Rio Grande have left us valuable information regarding a natural environment long since replaced by towns and cities, highways and railroad tracks, farms and ranches. This talk uses expedition journals and diaries to provide a sense of that long lost Texas and describe how Spanish colonial frontiersman began the process of environmental transformation in the San Antonio area.
Jesús F. de la Teja is Regents’ Professor Emeritus at Texas State University, where he taught history, and served as department chairman and as director of the Center for the Study of the Southwest. He obtained the Ph.D. in Latin American history from the University of Texas at Austin, and between 1985 and 1991 he worked in the Archives and Records Division of the General Land Office. He has published extensively on Spanish, Mexican, and Republic-era Texas, including Faces of Béxar: Early San Antonio and Texas (2016) and has served as book review editor for the Southwestern Historical Quarterly. He was the inaugural State Historian of Texas (2007-2009), is a Fellow of the Texas State Historical Association and of the Texas Catholic Historical Society, and is a member of the Texas Institute of Letters and the Philosophical Society of Texas. He currently serves as CEO of the Texas State Historical Association.
Caption (translation): Map of the place where the presidio and missions of San Antonio are located, where the province of Texas begins, and showing the extent of the surrounding woods. It is an area of very flat land. Original in the Archivo General de la Nación de México.
SESSION I 9:45 AM
HARDENING BY DESIGN SESSION INTRODUCTION Chair: Jeffrey Kauppila (Vanderbilt University)
I-1 9:50 AM
DFF Layout Variations in CMOS SOI – Analysis of Hardening by Design Options J. Black1, D. Black1, N. Domme1, P. Dodd1, P. Griffin1, R. Nowlin1, J. Trippe1, J. Salas1, R. Reed2, R. Weller2, A. Tonigan2, R. Schrimpf2 1. Sandia National Laboratories, USA 2. Vanderbilt University, USA
Four DFF layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 SOI process. SEU modeling and testing showed improved response with an increase in drain size and the use of shallow drain.
I-2 10:05 AM
Improving the Reliability of TMR with Non-Triplicated I/O on SRAM FPGAs M. Cannon, A. Keller, H. Rowberry, C. Thurlow, A. Pérez-Celis, M. Wirthlin Brigham Young University, USA
This work examines the trade-offs between common-IO and triplicated-IO TMR systems and demonstrates several mitigation techniques that improve the neutron cross-section from 2x to 26x with minimum additional resource utilization.
I-3 10:20 AM
Applying Compiler-Automated Software Fault Tolerance to Multiple Processor Platforms J. Benjamin1, M. Wirthlin1, H. Quinn2, J. Goeders1 1. Brigham Young University, USA 2. Los Alamos National Lab, USA
We present experimental data demonstrating our fully automated, compiler-based tool to add fault mitigation to user code, with neutron beam testing on RISC-V, ARM A9 and ARM A53 platforms.
10:35 - 11:05 AM Salons A-F, Pre-function area (foyer)
SESSION J 11:05 AM
HARDNESS ASSURANCE SESSION INTRODUCTION Chair: Thomas Turflinger (Aerospace Corporation)
J-1 11:10 AM
Risk Methodology for SEE Caused by Proton-Induced Fission of High-Z Materials in Microelectronics Packaging R. Ladbury NASA GSFC, USA
Proton-induced fission of high-Z materials can produce high fluxes of high-LET ions in microelectronics. We develop methods to evaluate risks for a range of destructive and nondestructive SEE modes caused by this threat.
J-2 11:25 AM
Data Retention Voltage Based Analysis of Systematic Variations in SRAM SEU Hardness: A Possible Solution to Synergetic Effects of TID D. Kobayashi1, K. Hirose1, K. Sakamoto2, S. Okamoto2, S. Baba2, H. Shindou2, O. Kawasaki2, T. Makino3, T. Ohshima3, Y. Mori4, D. Matsuura4, M. Kusano4, T. Narita4, S. Ishii4 1. ISAS/JAXA and Univ. of Tokyo, Japan 2. R&D/JAXA, Japan 3. QST, Japan 4. MHI Ltd., Japan
SEU cross-section is known to acquire post-silicon variation by TID. This issue is studied through a voltage parameter easily available in SRAMs. Results show its potential to predict and cancel out the variations in flight.
J-3 11:40 AM
Single Event Latchup Sensitive Volume Model for a 180-nm SRAM Test Structure P. Wang1, A. Sternberg1, B. Sierawski1, E. Zhang1, N. Dodds2, G. Vizkelethy2, S. Jordan3, D. Fleetwood1, R. Reed1, R. Schrimpf1 1. Vanderbilt University, USA 2. Sandia National Laboratories, USA 3. Jazz Semiconductor Trusted Foundry, USA
New ion-induced latchup data and previous laser-induced latchup data facilitates the definition of a multiple, nested sensitive-volume model using the Monte Carlo Radiative Energy Deposition tool. Hardness assurance implications are discussed.
J-4 11:55 AM
Energy-Dependent Effective Cross Sections of Neutron Interactions with Semiconductor Devices S. Wender1, J. O’Donnell1, L. Zavorka1, B. Bhuva2 1. Los Alamos National Laboratory, USA 2. Vanderbilt University, USA
We have developed a technique to measure the neutron beam attenuation through a stack of PCBs. This will allow test engineers to correct inaccuracies in the failure-in-time (FIT) rate measurements during SEU tests.
J-5 12:10 PM
Evaluating Elevated Temperature DRAM Stuck Bit Sensitivity at Room Temperature S. Guertin1, W. Parker1, D. Nguyen1, S. Delaney2, P. Blaisdell-Pijuan3, J. Vanacore4, G. Allen1, D. Sheldon1 1. Jet Propulsion Laboratory, USA 2. San Diego State University, USA 3. Princeton University, USA 4. California Polytechnic State University, USA
High temperature measurements anneal stuck bits in test devices, invalidating results. Impact is exacerbated in low- to moderate-temperature, high-dose missions. A low-temperature method is presented for mission estimates.