A one day Short Course “Techniques For SEE Modeling and Mitigation” will be presented at the 2016 IEEE Nuclear and Space Radiation Effects Conference (NSREC). This course will provide an introduction into the many issues involved in modeling and mitigating radiation-induced single event effects (SEE) in terrestrial and space environments, with an emphasis on Soft Error Rate (SER) and Single Event Transient (SET) reliability. The course will be beneficial to those new to the field, by introducing the basic concepts before discussing advanced and emerging issues. It will also benefit those already experienced in the field through the introduction of novel CMOS devices and an update on space radiation environment modeling and SEE modeling and mitigation techniques.
The Short course is organized into four sections, beginning with an overview of CMOS device scaling, from Bulk and SOI planar, to FinFET transistors, and the advantages that some of these advanced technology nodes may have in a space radiation environment. The second section deals with an overview of the the space radiation environment, specifically for near-Earth missions, and the many radiation sources that one needs to take into account. The third and fourth sections take an in depth look at the specific radiation environment on SER (third section) and SEE (fourth section) from a modeling perspective. In section three, modeling of the device and circuit-cell SER in neutron and in heavy ion environments will be explored, from a general framework to that required for advanced SOI CMOS devices (including FinFETs). Finally, in section four the single event modeling issues required for radiation hardness by design (RHBD) will be discussed with an emphasis on the typical tools found in ASIC design flows.
The course is intended for designers, radiation engineers, component specialists, and other technical and management personnel who are involved in developing reliable systems designed to operate in radiation environments. The course provides a unique opportunity to NSREC attendees to benefit from the expertise of the instructors, as well as the in-depth coverage and application-oriented perspective provided by the Short Course format. Electronic copies of in-depth notes will be provided at registration.
Continuing Education Units (CEUs)
For those interested in Continuing Education Units (CEUs), there will be an open-book exam at the end of the course. The course is valued at 0.6 CEUs, and is endorsed by the IEEE and by the International Association for Continuing Education and Training (IACET).
Short Course Chairman
Ken Rodbell Short Course Chairman
Ken Rodbell is a Principal Research Staff Member and manages Soft Error Rate (SER) research at the IBM Thomas J. Watson Research Center in Yorktown Heights, NY. He received his B.S. (1982), M.S. (1983) and Ph.D. (1986) in Materials Science and Engineering, with a minor in statistics, from Rensselaer Polytechnic Institute. His technical interests have focused on Si based electronic materials; including thin film metallurgy, crystallographic texture, electromigration, and radiation induced soft errors in semiconductor devices (including the first definitive paper characterizing low energy proton induced fails in 65 nm SOI and the use of stacked latches to reduce SER in 32 nm SOI). He has co-authored more than 80 issued U.S. patents. He was one of a team recognized as the New York State 2006 Inventor of the Year for a Cu plating technology patent. Ken is a Senior Member of the IEEE.
Jerome Mitard received the Ph.D. degree in microelectronic engineering from the Polytechnic University School of Marseille, France, in 2003. For three years, he acted as an STMicroelectronics assignee with CEA-LETI, Grenoble, France, where he was deeply involved in the electrical characterization of hafnium-based dielectrics with metal gate for sub-70 nm complementary metal–oxide–semiconductor (CMOS) technologies. After his Ph.D. in microelectronics at Micro and Nanotechnologies Campus Center, Grenoble, France, he joined the IMEC R&D center in Belgium, as a device researcher working on high-mobility devices for sub-10nm FinFET technology. He is currently team leader in charge of the Platform Device Research at IMEC.
Device Scaling Jerome Mitard IMEC
Dr. Jerome Mitard, from IMEC R&D center, will present a short course on advanced technology options required to achieve high speed operation and multiple functions of circuits designed for various terrestrial or spatial applications. This short course will be split into three parts going from general device scaling considerations down to a specific case study in which the impact of space radiation is addressed. Novel architectures like FinFET and gate-all-around combined with high-mobility channels will be extensively discussed since they offer a promising path to continue the device scaling while improving the intrinsic device performance further. Lastly, a deep dive into the development of strained Ge pFETs will close this course, showing how this development can serve the interest of the space radiation effects community.
Introduction Can the device scaling serve the development of space technologies? Transistor scaling : Transistor scaling “to infinity ... and beyond” ? How do we support Moore’s law nowadays? Changing materials Changing device architectures What’s beyond CMOS? Case study: strained Ge pFinETs. From TCAD simulations to state-of-the-art high-mobility devices. Conclusions
Paul O’Brien is a Research Scientist in the Space Sciences Department at The Aerospace Corporation, where he has been since 2002. He conducts scientific research into the Earth’s radiation belts and magnetosphere. He also develops space environment models and tools for satellite design, situational awareness, and anomaly resolution. He has a B.A. degree from Rice University in Physics and Classics, and M.S. and Ph.D. degrees from UCLA in Geophysics and Space Physics.
Space Radiation Environment Paul O'Brien The Aerospace Corporation
Paul O’Brien, The Aerospace Corporation, will present a short course on the space radiation environment, with emphasis on topics relevant to space system design and operation for near-Earth missions. We begin with an overview of the radiation environment and its effects, followed by a brief description of how designers and operators approach the problems caused by that environment. We survey energetic plasma, trapped electrons, trapped protons, solar energetic particles, and galactic cosmic rays. For each topic we describe the location, phenomenology, effects, design specification approaches, operational considerations, and areas of active research. We also discuss small sensors designed to provide situational awareness and support further improvement of design specifications. We show that new orbits, new materials, and new technologies drive a need for continued improvement in models and sensors to support space system design and operation.
Klas Lilja is the founder and CEO of Robust Chip Inc. (RCI), a company specialized in analysis of radiation effects in electronics and design of radiation hard electronics. He received M.Sc. and Ph. D. degrees from Chalmers Technical University, Sweden, and the Swiss Federal Institute of Technology (ETH), Switzerland, in 1986 and 1992 respectively, and has over 25 years of experience in the area design, simulation and radiation hardening of electronic devices and circuits. Prior to founding RCI, Klas was VP Engineering at ISE and Head of TCAD at Avant! Corporation (both companies are now part of Synopsis). As founder of RCI, he has led the development of RCI’s unique software tools and break-through technology for radiation hardened electronics, and developed the company into a worldwide leader in this field. Klas holds more than 10 issued and pending patents on RCI’s new technology, as well as several other patents in the area of semiconductor devices and semiconductor simulation.
Environment & Devices, SER - "Modeling Neutrons & Heavy Ion SER, From Planar CMOS to FinFETs" Klas Lilja Robust Chip Inc.
Dr. Klas Lilja, Robust Chip Inc., will discuss methods, techniques, and tools for single event error rate prediction. This short course will focus primarily on the device and circuit-cell, and will review various approaches to SER prediction, ranging from the classic RPP (sensitive volume) method to the most accurate state-of-the-art techniques. This class will give an overview of the tools and modeling techniques involved, including particle Monte Carlo and device- and circuit simulation, describe cross-section and error rate calculation, and show how different radiation environments are handled in the predictions.
The advantages and short-comings of the various error rate prediction methods for application in today’s most advanced FinFET and SOI technologies will be discussed, as well as their application in the process of optimizing and hardening a design in these technologies. Based on application examples, the key information that a designer can get from SER prediction, the expected accuracy of the information, and how it can be used in hardening of the design, will be discussed. Finally, a brief overview of how the cell level SER information supports full chip/system SER analysis, prediction, and potential hardening, will be given.
Introduction to Single Event Effects
Review of SER prediction methods
Modeling techniques for SER prediction
From energy deposition to circuit response (Monte Carlo-, device-, and circuit- simulation)
Calculation of error rates for different circuits and environments
Advanced topics in SER prediction
Advanced technologies and device geometries (bulk vs. SOI/FinFET)
Charge sharing, angular dependence, sub LET-threshold effects, and SER at near/sub threshold conditions
The use of SER prediction in radhard-by-design (RHBD)
Comparison to experimental results – how good is today’s SER prediction?
Jeff Kauppila is a Senior Research Engineer with Vanderbilt University’s Institute for Space and Defense Electronics (ISDE), where he works in the area of radiation effects modeling and radiation-hardened design for microelectronics. He received his Ph.D. in Electrical Engineering (2015), M.S. in Electrical Engineering (2003), and his B.E. in Electrical Engineering (2001) all from Vanderbilt University. Dr. Kauppila joined ISDE in 2003 and his research focuses on the development of radiation-effects-enabled compact models, integration of models with existing- and custom-developed process-design-kits (PDK), and the application of the radiation-enabled models in the design of radiation-hardened strategic defense systems electronics. Dr. Kauppila is actively involved in the development and design of integrated circuits and test structures used to extract and calibrate electrical and radiation-enabled model parameters. Dr. Kauppila has analog/mixed signal design experience in bipolar junction transistor, bulk CMOS, silicon-on-insulator CMOS, and FinFET technologies with minimum process feature sizes from 6 μm down to 14 nm. Dr. Kauppila is a licensed professional engineer in the state of Tennessee.
Environment & Devices, SEE - "Single Event Modeling for Rad-Hard-By-Design Flows" Jeff Kauppila Vanderbilt University Institute for Space and Defense Electronics
Dr. Jeff Kauppila, Vanderbilt University Institute for Space and Defense Electronics, will discuss the use of single-event modeling and simulation in the design of radiation-hardened-by-design (RHBD) circuits. The escalating costs to fabricate modern RHBD ASICs require engineers to consider radiation effects early in the physical design phase through modeling and simulation. The presentation will focus on recent advancements in single-event modeling of transients and upsets through circuit simulation. Model topologies, attributes, and limitations will be discussed. Techniques utilized to calibrate and validate the behavior of single-event models will also be discussed. The presentation will conclude with a discussion of the use of single-event models in RHBD optimization, and the integration of radiation-enabled models within the typical tools found in rad-hard ASIC design flows.
Introduction and overview
Traditional / historical SEE modeling techniques
Trends and techniques in SEE compact modeling
Bias-dependence of single-event currents
Bulk technology modeling
SOI technology modeling
FinFET technology modeling
Calibration and validation of SEE compact models
Model calibration with 3-D TCAD
SEE measurement for data-based validation
Application of SEE compact models in rad-hard-by-design flows