Technical Program 2025 – Session F

2025 IEEE NSREC TECHNICAL PROGRAM

SESSION F SCHEDULE

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

THURSDAY, JULY 17, 2025

SESSION F

Grand Ballroom 2-3

BASIC MECHANISMS OF RADIATION EFFECTS

9:30 AM

SESSION INTRODUCTION

Chair: Giulio Borghello, CERN

F-1

9:35 AM

Gamma Ray Induced Displacement Damage in Silicon Microvolumes: Single Defect Generation Rate and Random Telegraph Signal

V. Goiffon1, C. Durnez2, A. Antonsanti1, A. Jouni3, V. Lalucaa2, A. Jay4, D. Lambert5, T. Jarrin5, R. Monflier4, N. Richard5, P. Paillet5, C. Virmontois2

  1. ISAE-SUPAERO, France
  2. CNES, France
  3. Sodern, France
  4. LAAS, CNRS, France
  5. CEA, France

The expression of single displacement damage defects induced by 60Co gamma-rays is revealed in silicon microvolumes using a state-of-the-art CMOS pixel array. The creation of gamma induced bulk random telegraph signal is also evidenced.

F-2

9:50 AM

Differences in TID Response when Irradiating Highly-Scaled MOSFETs with 10 keV X-rays versus 1 MeV Gammas

J. Kauppila1, G. Poe1, T. Haeffner1, J. Laporte1, M. Siath1, S. Vibbert1, C. Moyers1, M. Evans1, D. Vibbert1, C. Conte1, A. Vidana2, N. Dodds2, N. Nowlin2, P. Oldiges2, K. Sapkota2, J. Joffrion2, T. Wallace3, H. Barnaby3, L. Massengill1

  1. Reliable MicroSystems, LLC, USA
  2. Sandia National Laboratories, USA
  3. Arizona State University, USA

Experiments on three highly-scaled technologies show that 10-keV X-rays cause far more TID degradation than 1-MeV gammas, even when irradiating to the same dose. The underlying mechanism is being identified to inform hardness assurance guidelines.

F-3

10:05 AM

SQUID GAME: Gamma, Atmospheric, and Mono-Energetic neutron effects on a quantum device

G. Casagranda1, C. Cazzaniga2, M. Kastriotou2, C. Frost3, F. Vella1, P. Rech1

  1. University of Trento, Italy
  2. STFC, United Kingdom
  3. ISIS Neutron and Muon Facility, United Kingdom

We present data from 14MeV and atmospheric-like neutron experiments on a SQUID. We characterize the radiation impact on the quantum device and find that neutrons and background gammas can generate peak or burst I-V perturbations.

2025 IEEE NSREC POSTER SESSION F

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

WEDNESDAY, JULY 16, 2025

2:50 PM – 4:50 PM

Germantown 1-3

PF-1     TID Degradation Mechanisms in Gate-All-Around Silicon Nanowire FETs

C. Champagne1, D. Ball1, J. Trippe1, R. Ritzenthaler2, J. Mitard2, D. Linten2, L. Massengill1, S. Kosier1, R. Reed1, E. Zhang3, M. Alles1, S. Bonaldo4, D. Fleetwood1, B. Sierawski1

  1. Vanderbilt University, USA
  2. imec, Belgium
  3. University of Central Florida, USA
  4. University of Padova, Italy

TCAD analysis of the contributions of gate and spacer oxides to the measured TID response of nanowire FETs indicates that the gate oxide is a significant degradation driver. Results are com-pared with previous technology nodes.

PF-2     An Implicit Radiation-Aware Surface Potential Model for FDSOI CMOS Technologies

I. Livingston1, I. Esqueda1, H. Barnaby1, M. Spear1, J. Solano1, T. Wallace1

  1. Arizona State University, USA

An implicit defect-based surface potential model is presented for fully-depleted silicon-on-insulator MOSFETs. The accuracy of this model is compared to experimental data on devices from a commercial 22nm FDSOI process after total ionizing dose exposure.

PF-3L    Total-Ionizing-Dose Effects and Low-Frequency Noise in 90 nm Bulk CMOS Devices

Neuendank1, T. Kirby1, H. Barnaby1, D. Fleetwood2, S. Bonaldo3, D. Loveless4, S. Westfall4, P. Muscat1, M. Nour5, M. Chambers5

  1. Arizona State University, USA
  2. Vanderbilt University, USA
  3. University of Padova, Italy
  4. Indiana University, USA
  5. Skywater Technology, USA

The impact of 60Co gamma rays on the total ionizing dose DC response and random telegraph noise in bulk MOSFETs at 300 Kelvin is reported. Results show behavior is consistent with radiation-induced switching border/interface traps.

PF-4L    Si Thinning as a Hardening Technique Against SEU for 28-nm Bulk CMOS 6T SRAMs

Yazigi-Richoux1, H. Barnaby1, P. Kerber2, C. Saltonstall2, L. Andrus2, M. Marinella1, J. Neuendank1

  1. School of Electrical, Computer and Energy Engineering, Arizona State University, USA
  2. Sandia National Laboratories, USA

This work investigates how Si substrate thinning affects SEU sensitivity for 28nm process 6T SRAM cells. Both laser raster-scan data and TCAD simulation results are in qualitative agreement that thinning decreases the LET upset threshold.