2024 IEEE NSREC TECHNICAL PROGRAM SCHEDULE
SHAW CENTER, OTTAWA CANADA
OTTAWA SALON
FRIDAY, JULY 26, 2024
7:00 AM
Trillium Ballroom
Breakfast
INVITED TALK
8:00 AM – 9:00 AM
Ottawa Salon
TBD
SESSION H
HARDENING BY DESIGN
9:00 AM
SESSION INTRODUCTION
Chair: Dakai Chen (Zero-G Radiation Assurance)
H-1
9:05 AM
RHBD Current-Mode Bandgap with SET Isolation Using PVT-Independent Inverters
J. Cardenas Chavez1, T. Sandhu2, K. El-Sankary3, M. Yan3, A. Noguera Cundar1, L. Chen1
1. University of Saskatchewan, Canada
3. Dalhousie University, Canada
This manuscript introduces an SET insolation technique by using PVT-independent SET detectors and apply it into a current mode bandgap circuit to reduce the output SET magnitude. Simulation and proton experimental results revealed its effectiveness.
H-2
9:20 AM
12-bit High-Voltage Current-Steering-Assisted R-2R DAC with RCM and Parallel Switch for Satellite-Applications
C. Tahar1, C. Lee2, H. Kim3, K. Kwon3, S. Ryu1
1. Korea Advanced Institute of Science and Technology (KAIST), Korea, Republic of
2. Korea Advanced Institute of Science and Technology (KAIST), Korea Aerospace Research Institute (KARI), Korea, Republic of
3. Korea Aerospace Research Institute (KARI), Korea, Republic of
Circuit and architectural techniques for a RH high-voltage DAC are introduced. A prototype 12V 12-bit DAC with a current-steering-assisted R-2R configuration preserves the performance well up to 226-krad TID.
H-3
9:35 AM
Effects of Total-Ionizing-Dose Irradiation on Single-Event Upset for Double-SOI SRAM
S. Chen1, Y. Wang1, F. Liu1, B. Li1, J. Gao1, P. Zhao2, L. Wang1, J. Li1, C. Wang1, S. Ma1, G. Zhang1, Y. Liao1, P. Cui1, L. Gao1, H. Zhou1, C. Wang1, J. Liu2, J. Wan3, Y. Xu4, B. Li2, T. Ye2
1. Institute of Microelectronics, Chinese Academy of Sciences, China
2. Institute of Modern Physics, Chinese Academy of Sciences, China
3. State key lab of ASIC and System, Fudan University, China
4. College of Electronic and Optical Engineering, Nanjing University of Posts and Telecommunications, China
The single event upset cross-section is experimentally demonstrated to be enhanced by total ionizing dose due to increasing NMOS charge collection and reducing hold static noise margin. Back-gate biasing can significantly mitigate synergistic radiation damage.
SESSION I
SINGLE-EVENT EFFECTS: DEVICES AND INTEGRATED CIRCUITS
9:50 AM
SESSION INTRODUCTION
Chair: Daniel Limbrick (North Carolina A&T State University)
I-1
9:55 AM
1. UFRGS, Brazil
3. University of Trento, Italy
We test six vision transformer models and four micro-benchmarks on TPUs irradiated with neutrons. A greater number of heads and a higher residual blocks usage increase the model FIT rate while using convolutions reduces it.
I-2
10:10 AM
The Impact of Heavy-Ion Single Events on the Accuracy of SONOS Analog In-Memory
W. Donald1, P. Xiao2, M. Spear1, D. Hughart2, C. Bennet2, V. Agrawal3, H. Puchner3, A. Sapan2, M. Marinella1
1. Arizona State University, USA
2. Sandia National Laboratories, USA
3. Infineon Technologies, USA
The sensitivity of 40nm SONOS analog accelerator accuracy to single event effects from heavy ion irradiation is simulated, and a statistical model for these effects is discussed.
10:25 AM – 10:55 AM
RIDEAU CANAL ATRIUM
BREAK
I-3
10:55 AM
Single-Event Upset Laser Testing of Various SRAM Resources of a 7nm FinFET System-on-Chip and Correlation with Heavy Ion Data
S. Achaq1,2, V. Pouget2, L. Artola1, F. Manni3, A. Dufour3, J. Boch2
1. ONERA, France
2. IES, University of Montpellier, CNRS, France
3. CNES, France
We present the SEU laser testing of different SRAM resources of a 7nm FinFET programmable SoC. Results provide insights on the physical organization of the device and testing challenges are discussed. Correlation with heavy ion data is presented and discussed using charge collection modelling.
I-4
11:10 AM
Multiple-Cell Upset Analysis on 16/12-nm Bulk FinFET SRAM Caused by Proton Irradiation
K. Sakamoto1, K. Takeuchi1, Y. Tsuchiya1, N. Ohtani1, K. Kume2, S. Mizushima2, S. Sando2, S. Hatori2, T. Makino3, A. Takeyama3, T. Ohshima3, T. Kato4, R. Nakamura4, H. Shindou1
1. Japan Aerospace Exploration Agency, Japan
2. The Wakasa wan Energy Research Center, Japan
3. QST, Japan
4. Socionext Inc., Japan
The effects of proton-induced MCUs on 16 and 12-nm FinFET SRAMs were studied and compared with 20-nm bulk planar SRAM. We discovered that FinFET SRAMs have an advantage in MCU tolerance even with angular irradiation.
I-5
11:25 AM
Evaluation of SEU Cross-Section Trends for Threshold Voltage Options from the 16-nm to the 3-nm Bulk FinFET Nodes
Y. Xiong1, N. Pieper1, J. Kronenberg1, M. Delaney1, C. Nunez1, D. Ball1, M. Casey2, R. Fung3, S. Wen3, B. Bhuva1
1. Vanderbilt University, USA
3. Cisco, USA
SEU cross-section scaling trends for four bulk FinFET nodes are investigated using D-FF designs with different VT options at each node. Results show that SEU cross- sections vary significantly for different VT options at each node.
I-6
11:40 AM
1. University of Texas at Austin, USA
2. Air Force Research Laboratory, USA
A method of using hardware performance counters to characterize neutron cross section per cache access instead of per bit of the unmitigated Raspberry Pi 3B+ improves scaling accuracy of benchmarks to applications of other sizes.
I-7
11:55 AM
N. Baker1, E. Campbell1, M. Wirthlin1
1. Brigham Young University, USA
This paper presents a methodology for extracting additional insights from FPGA radiation tests using fault injection. Post-irradiation fault injection is applied to a complex FPGA design to identify the specific failure-inducing CRAM upsets.
12:10 PM – 12:15 PM
CONFERENCE CLOSING