Technical Program 2025 – Session A

2025 IEEE NSREC TECHNICAL PROGRAM

SESSION A SCHEDULE

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

TUESDAY, JULY 15, 2025

SESSION A

Grand Ballroom 2-3

SINGLE EVENT EFFECTS: DEVICES & ICs

9:05 AM

SESSION INTRODUCTION

Chair: Sapan Agarwal (Sandia National Laboratories)

A-1

9:10 AM

Key Variables in the Reliability of ML Models Exposed to Neutrons, Protons, and Heavy Ions

B. Coelho1, M. Saveriano1, M. Tali2, C. Frost3, M. Donetti4, M. Pullia4, E. Verroi5, F. Tommasino1, S. Bounasser6, C. Poivey2, P. Rech1

  1. University of Trento, Italy
  2. ESA, Netherlands
  3. ISIS Neutron and Muon Facility, United Kingdom
  4. CNAO, Italy
  5. TIFPA, Italy
  6. ESA, France

 

We test large machine learning models on TPUs at 5 different radiation facilities to identify particle, software, and hardware-dependent reliability behaviors and reduce the variable space to qualify the reliability of neural networks.

A-2

9:25 AM

Assessing System-Level SET Response in Analog PLLs from Component-Level Response

D. Sam1, J. Teng2, B. Ringel1, P. Francis1, J. Moody1, J. Shin1, Z. Brumbach1, A. Ildefonso3, A. Khachatrian4, T. Crane5, D. Mcmorrow4, J. Cressler1

  1. Georgia Institute of Technology, USA
  2. The Aerospace Corporation, USA
  3. Indiana University Bloomington, USA
  4. US Naval Research Laboratory, USA
  5. Jacobs, Inc. and US Naval Research Laboratory, USA

The SETs of standalone circuits of a fully analog SiGe PLL are used to understand system-level SET responses and determine the circuit whose SET response is the most impactful to the output of the PLL.

A-3

9:40 AM

One-Fin versus Two-Fin Single Event Upset Vulnerability at the 3-nm Bulk FinFET Technology

S. Tolson1, J. Kronenberg1, N. Pieper1, Y. Xiong1, D. Ball1, B. Bhuva1

  1. Vanderbilt University, USA

Single-event upset cross-sections are investigated as a function of the number of fins in a transistor at the 3-nm node. Results show that one-fin D-FF designs are less vulnerable than similar two-fin D-FF designs under identical conditions

2025 IEEE NSREC POSTER SESSION A

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

WEDNESDAY, JULY 16, 2025

2:50 PM – 4:50 PM

Germantown 1-3

PA-1    The Research on 22 nm UTBB-FDSOI SRAM MCUs with Staggered Well under Back-Bias of 0 V

L. Tongde1, Z. Yuanfu2, Z. Yong-qin1, Y. Jing-shuang1, A. Paccagnella3, W. Liang1

  1. Beijing Microelectronics Technology Institute, China
  2. China Academy of Aerospace Electronics Technology, China
  3. University of Padua, Italy

This paper investigated the MCU characteristics of nano-scale FDSOI SRAM under different incident directions and angles. According to the experimental and numerical simulation results, the charge collection mechanisms were discussed.

 

PA-2    Neutron-induced Single Event Effects in 3D Managed NAND Memories

D. Peyronel1, G. Lama1, M. Valla1, M. Kastriotou2, C. Cazzaniga2, M. Bagatin3, S. Gerardin4

  1. Micron Semiconductor Italia Srl, Italy
  2. STFC, United Kingdom
  3. University of Padova, Italy
  4. DEI – Padova University, Italy

The sensitivity of 3D managed NAND Flash memories to atmospheric spectrum neutrons has been investigated, with a focus on the functional elements that lead to single event functional interrupts and user data corruption.

PA-3    Versal ACAP AI Engine Heavy Ion Testing with Spill Synchronization

Price1, G. Smith1, M. Wirthlin1

  1. Brigham Young University, USA

This work presents the heavy ion of the AI/ML engines within the Versal Core and Edge series devices. This approach tests the hundreds of AI engines within these devices simultaneously and synchronously with beam spills.

PA-4    The Effect of Heavy Ions on Inference Accuracy on the IBM NorthPole

F. Viramontes1, V. Vergara2, A. Romero1, M. Spear3, W. Slater3, H. Quinn3

  1. UNM COSMIAC, USA
  2. Blue Halo, USA
  3. Air Force Research Laboratory, USA

This abstract covers a heavy-ion test that was recently performed on the IBM NorthPole. SEFI and SEU cross sections of the device are discussed, as well as the effect of heavy-ions on AI/ML inference accuracy.

PA-5    Input and Clock State Dependence of D-FF SEU Vulnerability at 3-nm Bulk FinFET Node

J. Kronenberg1, N. Pieper1, Y. Xiong1, D. Ball1, B. Bhuva1

  1. Vanderbilt University, USA

SERs for D-FFs in a 3-nm technology show differences based on stored data, indicating state-dependent Qcrit values. Simulations show differences in charge collection by n- & p-hits, and design asymmetry are primary factors determining state-dependent SERs.

PA-6    Charge Generation Correlation in Silicon PN Diodes for Heavy Ions vs. Two-Photon Absorption

R. Rodriguez-Davila1, A. Carillo-Osuna1, T. Moise1, B. Gnade1, R. Baumann1, M. Quevedo-Lopez1

  1. The University of Texas at Dallas, USA

Bessel-focusing two-photon absorption (TPA) in silicon diodes accurately simulates the effects of heavy ion radiation, offering a cheaper and more accessible alternative for evaluating single event effects in semiconductor devices.