2026 IEEE NSREC TECHNICAL PROGRAM

SESSION H SCHEDULE

PUERTO RICO CONVENTION CENTER, SAN JUAN, PR

FRIDAY, JULY 24, 2026

SESSION H
Ballroom A

HARDENING BY DESIGN

10:45 AM

SESSION INTRODUCTION
Chair: Nathan Nowlin (Sandia National Laboratories)

H-1
10:50 AM

A Novel Radiation-Hardened-by-Design FPGA 10T FinFET Configuration Cell Using High- Resistance Feedback

M. Reaz¹, N. Rezzak¹, V. Nguyen¹, J. McCollum¹, F. Hawley¹, E. Hamdy¹

1. Microchip Technology, USA

A novel RHBD 10T FPGA configuration cell in 12-nm FinFETs using 1.8V devices and a high- resistance RC feedback demonstrates SEU immunity from terrestrial-to-GEO environments, with TCAD identifying gate-oxide charge collection causing exceptionally rare high-LET SEUs.

H-2
11:05 AM

Impact of Topology on TID Response of 4th-Generation SiGe HBT Current Mirrors

Z. Brumbach¹, M. Hosseinzadeh¹, Q. Parker¹, D. Sam¹, B. Ringel¹, C. Ellis¹, Y. Mensah¹, P. Harris², M. McCurdy², R. Reed², J. Cressler¹

1. Georgia Institute of Technology, USA   2. Vanderbilt University, USA

TID effects on four distinct SiGe HBT current mirror topologies are analyzed. Simple and cascode current mirrors showed mild degradation, while Wilson and balanced-Wilson topologies did not. Circuit simulations were conducted to understand system-level impact.

H-3
11:20 AM

Comparing the SEE Response of Different RF Topological Design Choices Using Active RF Isolators

D. Sam¹, J. Caezza¹, J. Teng², B. Ringel¹, G. Tzintzarov², J. Cressler¹

1. Georgia Institute of Technology, USA   2. The Aerospace Corporation, USA

A pulsed-laser study compares the SEE response of two RF isolator topologies. Results demonstrate a reduced transient magnitude and duration in one of the topologies, and circuit simulations are leveraged to pinpoint SEE-resilient design choices.

H-4
11:35 AM

Radiation-Tolerant Analog In-Memory FFT Using Commercial Off-The-Shelf 176-Layer 3D NAND Flash

V. Shastry¹, J. Park¹, S. Seo², S. Kim², S. Yi¹

1. Texas A&M University, USA   2. University of Rhode Island, USA

Heavy-ion tolerant analog in-memory FFT computation is evaluated using commercial 176- layer TLC 3D NAND flash operated in SLC mode, where widened threshold voltage separation preserves FFT accuracy under heavy-ion exposure despite radiation-induced threshold voltage variability.

POSTER SESSION H

PH-1

Investigating Flux Dependent Fault Masking and Recoverability in a Mixed-Signal SoC via Spatial and Temporal Gating

A. Dwadasi¹, R. Rodriguez-Davila¹, M. Pate², T. Nikoubin¹, R. Baumann¹

1. University of Texas at Dallas, USA   2. Texas Instruments, USA

Flux dependent fault masking in a TI F28377D-SEP microcontroller is investigated using a high-speed shutter and 3-D printed physical masks, showing how temporal and spatial gating can expose hidden unrecoverable faults during accelerated SEE testing.

PH-2

Evaluation of single-event upset effects on VGG neural networks under model lightweighting and algorithm-level hardening

N. Yingqiang¹, T. Ming², Y. Guofang¹, C. Yaqing¹, C. Jianjun¹, L. Deng¹, Y. Jiaofen², L. Bin¹

1. National University of Defense Technology, China   2. Hunan University, China

This paper investigates SEU robustness of lightweight VGG networks using ReLU_max and L1-based algorithm-level hardening, evaluated via fault injection, heavy-ion, and laser experiments on sub-20 nm FinFET AI chips, revealing compression-dependent hardening effectiveness.