Technical Program 2025 – Session H

2025 IEEE NSREC TECHNICAL PROGRAM

SESSION H SCHEDULE

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

FRIDAY, JULY 18, 2025

SESSION H

Grand Ballroom 2-3

HARDENING BY DESIGN

9:30 AM

SESSION INTRODUCTION

Chair: Enxia Zhang, University of Central Florida

H-1

9:35 AM

Radiation-Hardened-by-Design Techniques to Mitigate Inductor-Originated Single-Event Frequency Transients in CMOS LC-Tank Oscillators

G. Adom-bamfi1, S. Biereigel2, E. Tackx1, P. Leroux1, J. Prinzie1

  1. KU Leuven, Belgium
  2. CERN, Switzerland

This work investigates RHBD techniques to mitigate SEFT in CMOS oscillators caused by single-event sensitivity in on-chip inductors. Heavy-ion microbeam tests on DCO circuits show that incorporating N+ islands and N-well layers reduces SEFT sensitivity.

H-2

9:50 AM

Design and Testing of a 32-Bit Radiation-Tolerant RISC-V Microcontroller Fabricated at the 22-nm FDSOI Node

C. Elash1, Z. Li1, J. Xing1, P. Pour momen1, D. Ramaswami1, D. Lambert1, J. Cardenas1, R. Fung2, S. Wen2, G. Martin3, L. Chen1

  1. University of Saskatchewan, Canada
  2. Cisco, USA
  3. QuickLogic Corporation, USA

A 32-bit RISC-V microcontroller is designed and fabricated at a 22-nm FDSOI node using Radiation Hardening by Design Techniques. Testing of the device shows remarkable tolerance to single event effects from protons and heavy ions.

2025 IEEE NSREC POSTER SESSION H

NASHVILLE RENAISSANCE HOTEL, NASHVILLE, TN

WEDNESDAY, JULY 16, 2025

2:50 PM – 4:50 PM

Germantown 1-3

PH-1    System-Level SEU Hardening of Wireless Receivers through Modulation Scheme Selection

J. Shin1, J. Teng2, Z. Brumbach1, B. Ringel1, D. Sam1, A. Ildefonso3, T. Crane4, A. Khachatrian5, D. Mcmorrow5, J. Cressler1

  1. Georgia Institute of Technology, USA
  2. The Aerospace Corporation, USA
  3. Indiana University Bloomington, USA
  4. Jacobs, Inc., USA
  5. US Naval Research Laboratory, USA

Pulsed-laser SEE testing is utilized to evaluate SEU-hardening of a SiGe wireless receiver through modulation scheme selection. Results demonstrate that intentionally selecting modulation schemes based on known component sensitivity can reduce system-level SEU rates.

PH-2    Total Dose Hardening Using a Sensitive Circuit Identification Methodology in a DC-DC Converter

M. Murillo1, R. Milner2, B. Dean1, J. D’amico1, T. Tengberg2, A. Witulski1, M. Alles1, S. Kosier1, J. Trippe1, T. Holman1, D. Ball1, M. Hu1, A. Fayed2, L. Massengill1

  1. Vanderbilt University, USA
  2. The Ohio State University, USA

Data-calibrated models of TID effects were used to simulate radiation effects in a DF-SIMO buck converter. Through this, a method of “sensitive circuit” identification was developed to efficiently simulate TID effects mitigation.

PH-3    Optimized Dynamic Back-Biasing Strategy to Improve TID Tolerance in Conventional-Well 22nm FDSOI Transistors

B. Dean1, M. Hu1, T. Haeffner2, J. Kauppila2, M. Alles1, J. Trippe1, D. Ball1, B. Sierawski1, T. Holman1, S. Kosier1, L. Massengill1

  1. Vanderbilt University, USA
  2. Reliable MicroSystems, USA

An optimizable back-biasing strategy for TID mitigation is presented based on 22nm FDSOI transistor data obtained with in situ back-bias variation, resulting in a calculated maximum survivable dose increase of over 35%.