2026 IEEE NSREC TECHNICAL PROGRAM

SESSION B SCHEDULE

PUERTO RICO CONVENTION CENTER, SAN JUAN, PR

TUESDAY, JULY 21, 2026

SESSION B
Ballroom A

SINGLE-EVENT EFFECTS: DEVICES AND INTEGRATED CIRCUITS

10:40 AM

SESSION INTRODUCTION
Chair: Ruben García Alía (CERN)

B-1
10:45 AM

LET and Orientation Dependent Angular SEU in 12-nm Bulk FinFET Flip-Flops

X. Lu1, J. Debnath2, E. Zhang2, J. Xing1, C. Elash1, D. Ramaswami1, Q. Chen1, L. Chen1

1. University of Saskatchewan, Canada   2. University of Central Florida, USA

Angular heavy-ion SEU cross-sections were measured for 12-nm FinFET flip-flops at 0° and 60° across multiple LETs and fin orientations. Results show increased σSEU under tilt, demonstrating scaling-dependent worst-case conditions and limitations of normal- incidence testing.

B-2
11:00 AM

Angular Dependence of Single Event Upsets in 3D NAND Flash Arrays with Very High Energy Ion Beams

M. Bagatin1, S. Beltrami2, A. Benvenuti2, A. Waets3, N. Emriskova3, R. Garcia3, S. Gerardin1

1. University of Padova, Italy   2. Micron Technology and Products Group, Italy   3. CERN, Switzerland

The effects of very-high-energy ions on 3D NAND Flash arrays are investigated. Cross sections at grazing angles, the spatial distribution, and clustering of radiation-induced errors are analyzed by exploiting the unique capabilities of high-energy beams.

B-3
11:15 AM

Reliability of Processing-in-Memory Accelerators for Deep Neural Networks Inference

M. Wagner1, F. Santos1, M. Traiola1, P. Rech2, A. Kritikakou1

1. INRIA, France   2. University of Trento, Italy

We present the first proton-irradiation campaign for a commercial processing-in- memory (PIM) AI accelerator executing end-to-end DNN inference. We report results from 10 DNN models and a microbenchmark, showing higher error criticality than conventional accelerators.

B-4
11:30 AM

Single-Event Leakage Current and Burnout in High-Voltage GaN and SiC PiN Diodes: A Comparative Analysis

G. Mayberry1, X. Zhao2, H. Gingold3, P. Maloney3, S. Islam1, A. Sengupta4, X. Shen5, A. Senarath1, O. Meilander1, B. Zhang2, S. Hankinson3, B. Bolton3, W. Hubbard6, S. Kosier1, T. Roy2, E. Zhang3, D. Fleetwood1, S. Pantelides1, M. Ebrish1, R. Schrimpf1

1. Vanderbilt University, USA   2. Duke University, USA   3. University of Central Florida, USA   4. DLR, Germany   5. University of Memphis, USA   6. NanoElectronic Imaging, Inc., USA

High-voltage GaN and SiC vertical PiN diodes were tested for SEEs at similar voltages for a wide LET range. The lower SEE tolerance of GaN is attributed to lower defect- multiplication activation energies.

B-5
11:45 AM

Mechanism of Heavy-Ion Induced Leakage Current in GaN HEMTs Buffer Layers

J. Gray1, S. Shorina2, J. Vielmette1, D. Ball1, E. Zhang2, P. Maloney2, H. Gingold2, B. Bolton2, S. Hankinson2, A. Billa2, H. Parra2, J. Trippe1, M. Alles1, S. Kosier1, D. Fleetwood1, R. Schrimpf1, L. Massengill1

1. Vanderbilt University, USA   2. University of Central Florida, USA

Heavy ion irradiation enhances leakage currents in GaN-based HEMTs. Experimental analysis confirms a permanent drain-to-source leakage path through the buffer layer under the gate, enabled by defect-assisted hopping.

B-6
12:00 AM

Single-Event Burnout of AlN Diodes under Heavy-ion Irradiation

C. Quiñones1, J. Osheroff2, P. Reddy3, S. Mita3, R. Kirste3, R. Collazo1, Z. Sitar1

1. North Carolina State University, USA   2. NASA Goddard Space Flight Center, USA   3. Adroit Materials, USA

Single-event burnout was observed in AlN Schottky barrier and p-n junction diodes under heavy-ion irradiation. Burnout thresholds decreased with increasing ion LET, similar to trends in other wide-bandgap semiconductors.

POSTER SESSION B

PB-1

Microdose-Induced Stuck Bits in 7-nm FinFET SRAMs

M. Gorbunov1, E. Timokhin1, J. Weijers1, M. Van de Burgwal1, L. Berti1, G. Thys1, T. Vervecken2, D. Van Nuffel2, T. Schulte2, J. Vanden Berk2, D. Geys2, S. Bounasser3, B. Glass3

1. IMEC, Belgium   2. Magics Technologies NV, Belgium   3. ESA, Netherlands

During the heavy-ion test campaign, we observed stuck bits in 7-nm FinFET SRAM blocks with certain bitcell types. The analysis and simulation results indicated that the microdose is the primary mechanism at typical fluence levels.

PB-2

Characterization of Spatial Variability of Single-Event Latch-up in a 14-nm FinFET Technology

S. Zhao1, X. Li1, D. Zhang1, B. Li1, R. Tang1, Y. Gao1, C. Yang1, P. Lu2, L. Shu1, J. Bu1, J. Gao1

1. Institute of Microelectronics of the Chinese Academy of Sciences, China   2. Ocean University of China, China

The significant spatial heterogeneity of SEL characteristics is revealed in a 14-nm FinFET multi-core SoC through heavy-ion and pulsed-laser experiments. A differentiated hardening strategy linking sensitivity to body-tie distance is proposed to provide design guidance.

PB-3

Effects of Electrical Program/Erase Cycling on the Single-Event Response of 65-nm SONOS Charge-Trap NOR Flash Memory

A. Hubbard1, A. Murali2, H. Hunnicutt1, T. Peyton1, B. Ray2, A. Ildefonso1, D. Loveless1

1. Indiana University Bloomington, USA   2. Colorado State University, USA

Heavy‑ion testing on 65‑nm MirrorBit SONOS Charge-Trap NOR flash memory showed that program/erase‑cycled sectors exhibit significantly lower bit‑normalized SEU cross- sections compared to single‑programmed sectors.

PB-4

Mechanism Study of Heavy-Ion SEEs in a 12-bit SAR ADC in 22-nm FD-SOI

J. Zhao1, Z. Li1,2, Q. Ma1, Y. Qing1, M. Gorbunov2, M. Zhang1, E. Tackx1, J. Prinzie1, P. Leroux1

1. KU Leuven, Belgium   2. IMEC, Belgium

22-nm FD-SOI SAR ADC heavy-ion tests reveal outliers at LET 27.5–60.2. Errors map to sampling, control, comparator, and flip-flop SEEs. As cross-section rises, signatures migrate from single-mechanism to arbitrary multi-bit and mixed-mechanism errors

PB-5

Reliability of Image Classification and Object Detection on Embedded Systolic Arrays

P. Foletto Pimenta1, S. Savazzi2, E. Verroi3, M. Pullia2, F. Santos4, P. Rech1

1. University of Trento, Italy   2. Centro Nazionale di Adroterapia Oncologica, Italy   3. Trento Institute for Fundamental Physics and Applications, Italy   4. INRIA, France

We investigate the impact of 200 MeV protons on convolutions and prediction tasks executed on Tensor Processing Units. Kernel size does not impact output correctness while detection shows significantly more critical errors than classification.

PB-6
12:15 PM

Characterization of Latent Gate Damage and Single-Event Leakage Current by Gate Charge Measurements of Irradiated Silicon Carbide Power MOSFETs

A. Sengupta1,2, R. Cadena2, J. Vielmette2, S. Islam2, X. Zhao3, D. Bal2, A. Sternberg2, J. Osheroff4, J. Hutson5, M. Alles2, K. Galloway2, A. Witulski2, R. Schrimpf2, S. Kosier2

1. DLR, Germany   2. Vanderbilt University, USA   3. Duke University, USA   4. NASA Goddard Space Flight Center, USA   5. Lipscomb University, USA

Gate charge measurements reveal that latent gate damage and drain-gate single-event leakage current in SiC MOSFETs are strongly dependent on the particle energy and drain bias during irradiation and are precursors to single-event gate rupture. – LUNCH in PRCC Level 1 – Exhibit Hall A and Young Professionals (YP) LUNCHEON at the Sheraton Hotel SESSION C Photonics Devices and Integrated Circuits SESSION INTRODUCTION Chair: Julien Mekki (CNES)